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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT393 Dual 4-bit binary ripple counter Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Dual 4-bit binary ripple counter FEATURES * Two 4-bit binary counters with individual clocks * Divide-by any binary module up to 28 in one package * Two master resets to clear each 4-bit counter individually * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT393 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. 74HC/HCT393 The 74HC/HCT393 are 4-bit binary ripple counters with separate clocks (1CP and 2 CP) and master reset (1MR and 2MR) inputs to each counter. The operation of each half of the "393" is the same as the "93" except no external clock connections are required. The counters are triggered by a HIGH-to-LOW transition of the clock inputs. The counter outputs are internally connected to provide clock inputs to succeeding stages. The outputs of the ripple counter do not change synchronously and should not be used for high-speed address decoding. The master resets are active-HIGH asynchronous inputs to each 4-bit counter identified by the "1" and "2" in the pin description. A HIGH level on the nMR input overrides the clock and sets the outputs LOW. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay nCP to nQ0 nQ to nQn+1 nMR to nQn fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". maximum clock frequency input capacitance power dissipation capacitance per counter notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 12 5 11 99 3.5 23 20 6 15 53 3.5 25 ns ns ns MHz pF pF HCT UNIT December 1990 2 Philips Semiconductors Product specification Dual 4-bit binary ripple counter PIN DESCRIPTION PIN NO. 1, 13 2, 12 3, 4, 5, 6, 11, 10, 9, 8 7 14 SYMBOL 1CP, 2CP 1MR, 2MR 1Q0 to 1Q3, 2Q0 to 2Q3 GND VCC NAME AND FUNCTION 74HC/HCT393 clock inputs (HIGH-to-LOW, edge-triggered) asynchronous master reset inputs (active HIGH) flip-flop outputs ground (0 V) positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Product specification Dual 4-bit binary ripple counter 74HC/HCT393 Fig.4 Functional diagram. Fig.5 State diagram. COUNT SEQUENCE FOR 1 COUNTER OUTPUTS COUNT Q0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Notes Fig.6 Logic diagram (one counter). 1. H = HIGH voltage level L = LOW voltage level 4 L H L H L H L H L H L H L H L H L L H H L L H H L L H H L L H H Q1 L L L L H H H H L L L L H H H H Q2 L L L L L L L L H H H H H H H H Q3 December 1990 Philips Semiconductors Product specification Dual 4-bit binary ripple counter DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER 74HC/HCT393 TEST CONDITIONS UNIT V WAVEFORMS CC (V) ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.7 +25 -40 to +85 max. 155 31 26 55 11 9 175 35 30 95 19 16 100 20 17 100 20 17 5 5 5 5 24 28 -40 to +125 min. max. 190 38 32 70 14 12 210 42 36 110 22 19 120 24 20 120 24 20 5 5 5 4 20 24 min. typ. max. min. tPHL/ tPLH propagation delay nCP to nQ0 tPHL/ tPLH propagation delay nQn to nQn+1 tPHL propagation delay nMR to nQn 41 15 12 14 5 4 39 14 11 19 7 6 80 16 14 80 16 14 5 5 5 6 30 35 17 6 5 19 7 6 3 1 1 30 90 107 125 25 21 45 9 8 140 28 24 75 15 13 ns Fig.7 ns Fig.8 tTHL/ tTLH output transition time ns Fig.7 tW clock pulse width HIGH or LOW master reset pulse width; HIGH removal time nMR to nCP maximum clock pulse frequency ns Fig.7 tW ns Fig.8 trem ns Fig.8 fmax MHz Fig.7 December 1990 5 Philips Semiconductors Product specification Dual 4-bit binary ripple counter 74HC/HCT393 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT 1CP 2CP 1MR 2MR UNIT LOAD COEFFICIENT 0.4 0.4 1.0 1.0 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 min. typ. tPHL/ tPLH tPHL/ tPLH tPHL tTHL/ tTLH tW tW trem fmax propagation delay nCP to nQ0 propagation delay nQn to nQn+1 propagation delay nMR to nQn output transition time clock pulse width HIGH or LOW master reset pulse width; HIGH removal time nMR to nCP maximum clock pulse frequency 19 16 5 27 15 6 18 7 11 6 0 48 -40 to +85 -40 to +125 max. 38 15 48 22 29 24 5 18 ns ns ns ns ns ns ns MHz 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.7 Fig.7 Fig.8 Fig.7 Fig.7 Fig.8 Fig.8 Fig.7 UNIT V WAVEFORMS CC (V) TEST CONDITIONS max. min. max. min. 25 10 32 15 24 20 5 22 31 13 40 19 December 1990 6 Philips Semiconductors Product specification Dual 4-bit binary ripple counter AC WAVEFORMS 74HC/HCT393 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the clock (nCP) to output (1Qn, 2Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the master reset (nMR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (nCP) removal time. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". December 1990 7 |
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